The default PCIe payload size on CM4 is 128 bytes. Everything works fine with 128 bytes. I would like to increase it to 512 bytes. By following this post:
viewtopic.php?t=314185
I was able to get lspci to show the desired result (pci_128.txt vs pci_512.txt in the attached). However, when I actually attempt to DMA a 256 byte packet from the CM4 to the FPGA, it does not work. The FPGA endpoint sends a MRD to the CM4 asking for 64 DWORDS (256 bytes) and it responds with a CPLD of only 32 DWORDS (128 bytes).
In the referenced post, it appears users were checking performance to see if it worked vs looking at actual PCIe packets.
But it appears that the pcie_bus_safe trick sets the PCIe config space correctly, but the CM4 root complex is not actually using it. Any ideas what I am missing?
viewtopic.php?t=314185
I was able to get lspci to show the desired result (pci_128.txt vs pci_512.txt in the attached). However, when I actually attempt to DMA a 256 byte packet from the CM4 to the FPGA, it does not work. The FPGA endpoint sends a MRD to the CM4 asking for 64 DWORDS (256 bytes) and it responds with a CPLD of only 32 DWORDS (128 bytes).
In the referenced post, it appears users were checking performance to see if it worked vs looking at actual PCIe packets.
But it appears that the pcie_bus_safe trick sets the PCIe config space correctly, but the CM4 root complex is not actually using it. Any ideas what I am missing?
Statistics: Posted by corestar — Sun Feb 04, 2024 2:31 am — Replies 0 — Views 71